WOLF develops XMC (Switched Mezzanine Card) graphics cards for video capture, process, encode and display. WOLF XMC video graphics boards can include an embedded NVIDIA GPU, AMD GPU and/or Xilinx FPGA.
Rugged air cooled and conduction cooled options are available for WOLF's XMC modules.
WOLF XMC Products Table
| Product Name | WOLF Number | GPU/Processor | Processing Speed (TFLOPS) | Memory (GB) | Outputs - DisplayPort | Outputs - SDI, Analog, Other | Inputs |
| XMC-P2000E-VO | 3176 | NVIDIA P2000E | 2.3 | 4 | 4 | ||
| XMC-E8860-VO | 0258 | AMD E8860 | 0.768 | 2 | 4 | 1 SVGA | |
| XMC-E9171-VO | 3196 | AMD E9171 | 1.25 | 4 | 5 | ||
| XMC-P2000E-SDI-CV | 3177 | NVIDIA P2000E | 2.3 | 4 | 4 | 2 SDI, 1 Analog | |
| XMC-E9171-CV | 3197 | AMD E9171 | 1.25 | 4 | 3 | 2 SDI | |
| XMC-E8860-SDI-CV | 3097 | AMD E8860 | 0.768 | 2 | 3 | 3 SDI, 1 Analog | |
| XMC-TK1-FGX | 30TP | NVIDIA Tegra K1 | 0.325 | 4 | 2 SDI, 1 HDMI | 2 SDI, 2 Analog | |
| XMC-FGX2-SDI-4IO | 3180 | WOLF FGX2 | 4 12G-SDI, VGA | 2 CXP, 2 12G-SDI, 3 Analog, 2 DP | |||
| XMC-FGX-SDI-4IO | 3080 | WOLF FGX | 4 SDI, 2 Analog | 2 SDI, 4 Analog, DP | |||
| XMC-P2000E-SDI-2IO | 3170 | NVIDIA P2000E | 2.3 | 4 | 3 | 2 SDI | 2 SDI, 2 Analog |
| XMC-E9171-SDI-2IO | 3190 | AMD E9171 | 1.25 | 4 | 3 | 2 SDI | 2 SDI, 2 Analog |
See the WOLF XMC Products Grid
XMC Information
The XMC mezzanine format defined in ANSI/VITA 42.0-2016 is an evolution of the previous PMC (PCI mezzanine card) format. The XMC specification extends PMC with the addition of new connectors which support gigabit serial interfaces plus alternative I/O standards.
The theoretical maximum power available on an XMC module is 100W. However, practical considerations normally require a lower XMC maximum operating power, with 25W being a typical maximum operating power.
The XMC connector is a pin-socket connector with 114 pins arranged in a 6 x 9 array. A single-width XMC module can have one or two 114 pin connectors (P15 and P16). It can optionally include PMC connectors (P11 to P14) for legacy compatibility. There are also provisions for a shortened depth card layout, with 124 to 139mm depths.
The primary XMC connector (P15) is reserved for serial links, power, and other pre-defined functions. The secondary XMC connector (P16) provides user-defined pins which can include video I/O.
XMC 1.0 connectors are defined in the VITA 42 XMC baseline specification, while XMC 2.0 connectors are defined in VITA 61.
- The XMC 1.0 and 2.0 connectors use the same footprint but are not intermateable.
- The XMC 2.0 connector was designed to be more rugged compared to the XMC 1.0 connector.
- The XMC 1.0 and 2.0 connectors support different clock speeds (and therefore, data throughputs).
- XMC 1.0 has been electrically characterized to support 3.125 GHz, providing support for PCIe 1.0 (which uses a clock speed of 2.5 GHz).
- XMC 2.0 has been electrically characterized to support 5 GHz with VITA 42 pin assignments, providing support for protocols such as PCIe 2.0 (which uses a clock speed of 5.0 GHz). It can support up to 7-12 GHz with alternate pin assignments.
- The XMC 2.0 connector is an off-white color, to make it easy to visually differentiate it from the black XMC 1.0 connector.
- The standard stacking height of an XMC 1.0 connector is 10mm (allowing it to fit on a carrier board with a slot pitch of 0.8 inch) or 12 mm (allowing it to fit on a carrier board with a slot pitch of 1.0 inch).
- The XMC 2.0 connector can also use a 15mm and 18mm stack height configuration (in addition to the 10mm or 12mm stack height configurations).
XMC Clock Speeds and PCIe Clock Speeds and Throughput
| Total Lanes | PCIe 1.0 | XMC 1.0 | PCIe 2.0 | XMC 2.0 | PCIe 3.0 | XMC 2.0 | PCIe 4.0 | |
| Clock (GHz) | 2.5 | 3.125 | 5.0 | 5.0 (with VITA 42 pin assignments) |
8.0 | 7 - 12 (with alternate pin assignments) |
16.0 | |
|
PCIe in each direction |
x1 | 0.25 | 0.5 | 0.98 | 1.97 | |||
| x4 | 1.0 | 2.0 | 3.94 | 7.88 | ||||
| x8 | 2.0 | 4.0 | 7.88 | 15.75 |
PCIe 1.0 and 2.0 uses an 8b/10b encoding scheme, resulting in a 20% (= 2/10) overhead on the raw channel bandwidth.
PCIe 3.0 and 3.0 uses a 128b/130b encoding scheme, resulting in a 1.54% (= 2/130) overhead on the raw channel bandwidth.